In a semiconductor memory device, improvement of signal propagation characteristics has become an important theme among various types of improvements of an operating speed of the semiconductor device. In a typical dynamic random-access memory (DRAM) product, correcting a duty cycle of an input signal and obtaining an output duty cycle of 50% by using a combination of a duty cycle detector (DCD) and a duty cycle corrector (DCC) have become a popular solution for improving the signal propagation characteristics. The DCD and the DCC as shown in FIG. 1 are circuits designed for correcting output waveforms. However, including the DCD and the DCC in semiconductor products such as DRAM may cause disadvantages such as a larger chip area for implementing the circuits and more power consumption due to increased electric currents to operate the DCD and DCC circuits.
In recent years, there has been an effort to correct the duty cycle. Adjusting a through rate of a clock signal by fine tuning of a bias level of transistors has been known. As another attempt, for example, WO2014/203775 A1 describes a highly noise-resistant high-precision duty regulator circuit including a plurality of clocked inverters. The plurality of clocked inverters coupled in parallel can be controlled independently, thus complexity of the DCC required for fine tuning of different bias levels can be reduced.